When designing a graphics system there are substantial cost advantages to be gained by minimizing amount of video random access memory (VRAM) used in the system display buffer. Several constraining factors dictate the absolute minimum amount of VRAM required in a particular system. The most important of these factors is the resolution of the system display. For example, a 1280.times.1024.times.8 display (i.e. a display arranged as an array of 1280.times.1024 pixels with 8 bits from the graphics processor defining each pixel) requires an absolute minimum of 1 1/4M bytes of VRAM.
Current display buffers are typically constructed with 256K.times.4 VRAM chips, therefore, if the display buffer is operating in conjunction with a 32 bit wide data bus, 8 VRAM chips are required per bank of memory. In this architecture, each bank provides 1 Mbyte of memory such that two banks are required to contain a 1280.times.1024.times.8 display. This disadvantageously leaves 3/4 Mbyte of display buffer memory unused by the system. Given that VRAM costs are determined primarily by the number of storage bits per chip, such a large number of unused bits represents significant unnecessary costs.
Thus the need has arisen for circuitry, systems and methods which reduce the amount of unused RAM in processing systems. In particular, by reducing the amount of unused VRAM in a given graphics system, the significant advantage of cost reduction is achieved since VRAM bit per bit is relatively expensive.